My attempt to learn OSDev writing a Microkernel for RISC-V https://blog.henrygressmann.de/series/os-dev/
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Henry Gressmann 58c64f176b
chore: update
Signed-off-by: Henry Gressmann <mail@henrygressmann.de>
2026-01-05 21:34:23 +01:00
.cargo chore: updates, remove paging 2024-02-12 22:50:12 +01:00
.vscode chore: update 2026-01-05 21:34:23 +01:00
crates chore: update 2026-01-05 21:34:23 +01:00
kernel chore: update 2026-01-05 21:34:23 +01:00
.gitignore a bunch of changes that didn't really work out in the end 2023-04-04 03:28:08 +02:00
Cargo.lock chore: update 2026-01-05 21:34:23 +01:00
Cargo.toml chore: update 2026-01-05 21:34:23 +01:00
LICENSE-APACHE feat: update simple_shell 2023-07-08 13:06:47 +02:00
LICENSE-MIT feat: update simple_shell 2023-07-08 13:06:47 +02:00
README.md chore: update deps 2024-08-01 19:58:53 +02:00
rust-toolchain.toml feat: kernel allocator 2023-03-29 22:38:18 +02:00
TODO.md a bunch of changes that didn't really work out in the end 2023-04-04 03:28:08 +02:00

License

This project is licensed under either of the following licenses, at your option:

Some code in the crates/riscv-mem directory is licensed under the GPL-3.0 license. See the LICENSE.md file for details.